1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to process monitor for CMOS integrated circuits.
2. Description of the Related Art
Fabrication of Complementary-Metal-Oxide-Semiconductor (CMOS) integrated circuits involves a large number of process steps that affect the N-type or NMOS transistors and other NMOS devices differently than P-type or PMOS devices. In order for the integrated circuit to operate properly, the relative electrical characteristics of the NMOS and PMOS devices must be within specified ranges. The relative qualities of the NMOS and PMOS devices, measured in terms of a figure of merit, is known in the art as the "process factor". Typically, the figure of merit is the switching speed of the device.
There are numerous parameters that can be varied during fabrication to cause NMOS devices to have higher merit, or be stronger, than PMOS devices and vice-versa. For this reason, a process monitor is integrally fabricated with each integrated circuit, and includes NMOS and PMOS transistors that are identical to those in the functional or logical devices of the circuit. The process monitor is preferably accessible via the standard input/output (I/O) pins of the integrated circuit, and enables measurement of the process factor of the circuit at various stages of the fabrication process.
For testing the process factor for a production run of integrated circuits, a set of test circuits are fabricated in which the processing parameters are varied in a known manner to produce the test circuits as having different process factors. The parameters are varied to produce at least one integrated circuit having strong NMOS and weak PMOS transistors (SNWP), weak NMOS and strong PMOS (WNSP) transistors, strong NMOS and strong PMOS (SNSP) transistors and weak NMOS and weak PMOS (WNWP) transistors.
The process factors of the test circuits are measured and plotted as illustrated in FIG. 1. The Y axis represents variation of fabrication parameters to selectively produce stronger NMOS transistors, whereas the X axis represents variation to selectively produce stronger PMOS transistors.
The four corners of the graph at SNWP, WNSP, SNSP and WNWP constitute the conceptual limits of process variation for the four extreme combinations of NMOS and PMOS transistors. In order to produce a CMOS integrated circuit with NMOS and PMOS transistors having the proper balance, the actual process factors for the set of test circuits must lie within a "region of acceptability" 10 as indicated by hatching in the drawing.
U.S. Pat. No. 5,068,547, entitled "PROCESS MONITOR CIRCUIT", issued Nov. 26, 1991 to William H. Gascoyne, is assigned to LSI Logic Corporation of Milpitas, CA, the assignee of the present invention. This patent discloses a monitor circuit for measuring the process factor for a production run of CMOS integrated circuits as discussed above.
The main elements of Gascoyne's monitor, designated as 12, are illustrated in FIG. 2. The monitor 12 comprises a delay unit 14 (delay unit A) and a delay unit 16 (delay unit B) that have inputs connected to receive input test pulses P.
The delay units 14 and 16 produce output pulses, designated as A and B, that are applied to inputs of an exclusive-OR gate 18 (equivalent results can be produced by replacing the gate 18 with an exclusive-NOR gate). The gate 18 produces a logically high output when the logical senses of the pulses A and B are different, and a logically low output when the logical senses of the pulses A and B are the same.
The delay units 14 and 16 are configured to alter the input pulses P to produce the output pulses A and B differently depending on the process factor of the integrated circuit under test, thereby enabling measurement of the process factor of the test set of integrated circuits.
More specifically, due to the slower carrier mobility of PMOS transistors as compared to NMOS transistors, certain types of CMOS logic gates, such as NOR gates, produce output pulses in response to input pulses in which the rising (positive-going) edges are sharper (delayed less) than the falling (negative-going) edges.
This causes the falling edges of the output pulses from a CMOS NOR gate to be delayed relative to the rising edges of input pulses by a longer period of time than the falling edges. This is due to the fact that the pull-up transistors in a CMOS NOR gate are PMOS, whereas the pull-down transistors are NMOS. The PMOS pull-up transistors pull up to the logically high level slower than the NMOS pull-down transistors pull down to the logically low level, thereby creating rising edge delays that are longer than falling edge delays.
The delay unit 16 comprises a chain of gates, preferably inverters, that differ from the above discussed NOR gates in that they have symmetrical rising and falling edges. In other words, the rising and falling edges are delayed by the same period of time. The purpose of the delay unit 16 is to provide a reference delay period such that the pulses B have essentially the same waveform as the input pulses P, but are delayed by a predetermined period of time.
The delay unit 14 comprises a chain of delay elements having the asymmetrical edge delay characteristics discussed above such that the rising edges are delayed more than the falling edges. Typically, the delay unit 14 comprises a chain of alternating NOR gates and inverters. There are more devices in the delay unit 14 than in the delay unit 16, such that the pulses A are delayed longer than the pulses B.
The operation of the prior art process monitor 12 is illustrated in the timing diagram of FIG. 3. The input pulses P have a period designated as Tin. The output pulses B from the delay unit 16 are delayed by a fixed length of time T1 from the respective input pulses P, and have a period Ta which is substantially equal to the period Tin of the input pulses P.
The output pulses A from the delay unit 14 have rising edges that are delayed by a length of time T2 from the respective input pulses P. The exclusive-OR gate 18 produces a logically high output when its inputs are different. Thus, the gate 18 produces an output signal OUT that is high during a period Wa between the rising edges of the output pulses A and B.
The falling edges of the output pulses B occur before the falling edges of the output pulses A, with the difference being a period Wb. The output signal OUT produced by the gate 18 is logically high during this time since the logical senses of the pulses A and B are different as described above.
The process factor is generally computed as being equal to the ratio of the periods Wa and Wb (Wa/Wb), although it can be subjected to normalization or other computation as described in the patent to Gascoyne.
Since the rising edges of the pulses A are affected by the strength of the PMOS transistors in the delay unit 14, the period Wa will increase as the strength of the PMOS transistors decreases, and vice-versa. The falling edges of the pulses A are affected by the strength of the NMOS transistors in the delay unit 14, and the period Wb will increase as the strength of the NMOS transistors decreases, and vice-versa. The graph of FIG. 1 is typically derived by plotting the ratio Wa/Wb on the vertical axis, and the average edge delay period [(rising edge delay period +falling edge delay period)/2] on the horizontal axis.
A major problem with the prior art process monitor 12 is that it is relatively insensitive to variations in process factor. For this reason, the delay units 14 and 16 must each comprise a very large number of gates in order to produce delay periods Wa and Wb that are sufficiently long to be accurately measured using currently available instrumentation.
The prior art process monitor requires so many gates that it typically occupies two input/output slots in a standard CMOS integrated circuit layout, in addition to substantial space in the core area of the layout. This limits the amount of space available for the actual logical circuitry of the CMOS integrated circuit.
In addition, the many gates of the process monitor 12 consume a large amount of power. This requires that a larger power supply be provided, or that the logical circuitry of the integrated chip be limited to provide the power required by the process monitor.